1. Field of the Invention
The present invention relates to a configuration of a voltage controlled oscillation circuit capable of variably controlling an oscillation frequency in accordance with a level of an externally applied voltage.
2. Description of the Background Art
In a large scale integrated circuit (referred to as xe2x80x9cLSIxe2x80x9d hereinafter), a clock generation circuit or the like which generates an internal clock signal synchronous with an external clock signal inside the LSI is often mounted so as to operate the internal circuit of the LSI synchronously with a clock applied from a system.
For such a clock generation circuit, a configuration in which an oscillation frequency of a self-excited oscillation type ring oscillator circuit is controlled so as to synchronize a phase of the oscillation output of this ring oscillator circuit with a phase of the external clock signal is sometimes employed. In order to allow the ring oscillator circuit to perform an oscillation operation while controlling the oscillation frequency of the ring oscillator circuit so as to synchronize the phase of the oscillation output of this ring oscillator circuit with the phase of the external clock signal, a so-called voltage controlled oscillation circuit (referred to as xe2x80x9cVCO circuitxe2x80x9d hereinafter) is employed.
FIG. 20 is a circuit diagram for describing a configuration of a conventional VCO circuit 8000.
VCO circuit 8000 is provided with an operating current control section 8100 which controls an operating current value in accordance with an external control voltage VIN, and a ring oscillator circuit 8200 which performs a self-excited oscillation operation with an operation current controlled by operation current control section 8100.
Operating current control section 8100 is provided with a P-channel MOS transistor TP01, an N-channel MOS transistor TN01 and a resistor R1 which are connected in series between a power supply potential Vcc and a ground potential GND, and a P-channel MOS transistor TP02 and an N-channel MOS transistor TN02 which are connected in series between power supply potential Vcc and ground potential GND.
A gate of transistor TP01 is connected to a gate of transistor TP02, and the gate of transistor TP01 is coupled to a drain of transistor TP01. Therefore, transistors TP01 and TP02 operate as a current mirror circuit. In addition, transistor TN01 receives control voltage VIN.
Operating current control section 8100 is further provided with a resistor R0 which is provided between the gate of transistor TP01 and ground potential GND.
On the other hand, ring oscillator circuit 8200 includes odd stages of inverters, e.g., three stages of inverters INV1 to INV3.
An output of inverter INV3 is applied to an input of inverter INV1 and cascaded inverters INV1 to INV3 perform self-excited oscillation operation.
Inverter INV1 is provided with a P-channel MOS transistor TP11, a P-channel MOS transistor TP12, an N-channel MOS transistor TN12 and an N-channel MOS transistor TNN11 which are connected in series between power supply potential Vcc and ground potential GND. A gate of transistor TP11 is coupled to a wiring LPV which is coupled to the gate of transistor TP01 (and the gate of transistor TP02). On the other hand, a gate of transistor TN11 is coupled to a wiring LNV which is coupled to the gate of transistor TN02. A gate of transistor TP12 is coupled to a gate of transistor TN12 and the output of inverter INV3 is applied to a coupling node thereof.
Inverter INV2 is provided with a P-channel MOS transistor TP21, a P-channel MOS transistor TP22, an N-channel MOS transistor TN22 and an N-channel MOS transistor TN21 which are connected in series between power supply potential Vcc and ground potential GND. A gate of transistor TP21 is coupled to wiring LPV. A gate of transistor TP22 and a gate of transistor TN22 are coupled to each other and receive a potential of an output node of inverter INV1. A gate of transistor TN21 is coupled to wiring LNV.
Inverter INV3 is provided with a P-channel MOS transistor TP31, a P-channel MOS transistor TP32, an N-channel MOS transistor TN32 and an N-channel MOS transistor TN31 which are connected in series between power supply potential Vcc and ground potential GND. A gate of transistor TP31 is coupled to wiring LPV. A gate of transistor TP32 and a gate of transistor TN32 are coupled to each other and receive a potential of an output node of inverter INV2. A gate of transistor TN31 is coupled to wiring LNV. The coupling node coupling transistor TP32 to transistor TN32 is an output node of inverter INV3 and this output node is connected to an input of inverter INV1. A potential of an output node of inverter INV3 is applied as an VCO output to the outside of VCO circuit 8000.
FIG. 21 is a graph showing the relationship between control voltage VIN of VCO circuit 8000 shown in FIG. 20 and an output clock frequency f (which relationship will be referred to as xe2x80x9cVCO characteristicxe2x80x9d hereinafter).
According to the characteristic shown in FIG. 21, VCO circuit 8000 is designed to serve to, for example, output a high frequency clock. The frequency characteristic of VCO circuit 8000 is expressed by a curve CA in FIG. 21. According to characteristic curve CA of VCO circuit 8000, VCO circuit 8000 outputs an arbitrary frequency between a minimum oscillation frequency fmin and a maximum oscillation frequency fmax, e.g., a frequency f1, to the outside of VCO circuit 8000 as a VCO output.
With the configuration of VCO circuit 8000, however, the frequency of the VCO output can be used as an oscillation frequency only within a determined frequency range (frequencies fmin to fmax). If VCO circuit 8000 oscillates with a low frequency of not more than minimum oscillation frequency fmin, in particular, the characteristic of VCO circuit 8000 disadvantageously becomes unstable. It is noted that an internal clock with such a relatively low frequency is necessary for LSI which generates an internal clock signal using a phased locked loop circuit (PLL circuit) including a VCO circuit to operate in, for example, a low consumption power operation mode.
Therefore, if an internal clock which oscillates with a frequency of not more than minimum oscillation frequency fmin, e.g., a frequency f2, it is necessary to separately provide another VCO circuit having a VCO characteristic expressed by a curve CB in FIG. 21.
Conventionally, therefore, it is disadvantageously difficult for one VCO circuit to simultaneously obtain a high frequency clock with frequency f1 shown in FIG. 21 and a low frequency clock with frequency f2 shown in FIG. 21.
To solve the above-mentioned disadvantages, Japanese Patent Laying-Open Nos. 7-74596, 3-259619 and 5-102801 disclose VCO circuits capable of controlling an oscillation frequency range more widely by setting the number of the stages of a ring oscillator circuit to be variable.
However, even these VCO circuits having the configurations described above have a disadvantage in that a circuit scale becomes relatively large so as to set the number of oscillation stages of the ring oscillator to be variable in an oscillation frequency region from low to high frequencies.
It is an object of the present invention to provide a voltage controlled oscillation circuit which has an easily controllable voltage controlled oscillation characteristic, and which can generate a high frequency internal clock and a low frequency internal clock while suppressing a circuit scale.
It is another object of the present invention to provide a voltage controlled oscillation circuit which enables a high frequency clock for high speed operation and a low frequency clock for a low consumption power operation to be outputted by one voltage controlled oscillation circuit.
In short, the present invention provides a voltage controlled oscillation circuit which is provided with a self-excited oscillation circuit and an operating current control circuit.
The self-excited oscillation circuit oscillates with a frequency in accordance with a level of an operating current control signal. The self-excited oscillation circuit includes a plurality of stages of inversion circuits connected in series, each having a field effect transistor as a switching element, and operating with a current in accordance with the operating current control signal. The operating current control circuit generates the operating current control signal in accordance with a control voltage applied from an outside of the voltage controlled oscillation circuit. The operating current control circuit includes a current mirror circuit and a current mirror control circuit. The current mirror circuit generates a constant current flowing from a first power supply node to a second power supply node, and outputs the operating current control signal in accordance with a value of the constant current. The current mirror control circuit controls the value of the constant current generated by the current mirror circuit in accordance with the control voltage, and changes a range, in which the value of the constant current is changed in response to a change of the control voltage, in accordance with an instruction signal applied from the outside of the voltage controlled oscillation circuit.
Therefore, the present invention has an advantage in that even if an internal clock with a high frequency is generated or an internal clock with a low frequency is generated, it is possible to generate a stable internal clock by using one voltage controlled oscillation circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.